Conventional hardware queuing techniques rely on a first-in first-out (FIFO) buffer to pass data output by a first processing unit as an input to a second processing unit. A FIFO buffer decouples the two processing units so that the second processing unit does not need to consume the data as the data is produced by the first processing unit. However, the size of the FIFO buffer is fixed and may fill requiring the first processing unit to stall and wait until the second processing unit begins draining the FIFO buffer. Processing throughput is reduced when the FIFO buffer is full and the first processing unit is stalled. Also, the data is removed from the FIFO buffer by the second processing unit in the same order in which the data was stored into the FIFO buffer by the first processing unit. For some systems, greater flexibility in terms of inserting and removing data from the FIFO buffer may be desired.
Thus, there is a need for addressing the issue of passing data between different processing units and/or other issues associated with the prior art.